A typical example of a pulse generating circuit is illustrated in FIG. 1. The pulse generating circuit comprises an oscillation circuit 1, a voltage divider 2, a comparator 3, a flip-flop circuit 4 and an AND gate 5. The oscillation circuit 1 comprises a series combination of a p-channel MOS field-effect transistor 6, a resistor 7 and an n-channel MOS field-effect transistor 8 coupled between a source line 9 of a positive voltage level V.sub.DD and a ground line 10 of the ground voltage level V.sub.G, a resistor 11 coupled between the drain node and the gate electrode of the MOS field-effect transistor 8 for providing an appropriate difference in voltage therebetween, a capacitor 12 coupled between the gate electrode of the MOS field-effect transistor 8 and the ground, a capacitor 13 coupled between the drain node of the MOS field-effect transistor 8 and the ground, and a crystal oscillator 14 coupled between the gate electrode and the drain node of the MOS field-effect transistor 8. The drain node of the MOS field-effect transistor 8 performs as an output node 15 of the oscillation circuit 1, and the output node 15 of the oscillation circuit 1 is coupled in parallel to one input node of the comparator 3 and an input node of the AND gate 5. The pulse generating circuit illustrated in FIG. 1 further has a control node 16 connected to the gate electrode of the MOS field-effect transistor 6 as well as a reset node of the flip-flop circuit 4 and an output node 17 to which a pulse train consisting of pulses each having a sufficient pulse height is supplied from an output node of the AND gate 5. The series combination of the MOS field-effect transistor 6, the resistor 7 and the MOS field-effect transistor 8 forms an amplification stage of the oscillation circuit 1.
The voltage divider 2 comprises a series of resistors 18 and 19 coupled between the source line 9 and the ground line 10 and is operative to produce a reference voltage level V.sub.REF which is constantly supplied to the other input node of the comparator 3. The voltage divider 2 thus arranged serves as a reference voltage producing circuit. The comparator 3 is operative to compare a voltage level at the one input node coupled to the output node 15 with the reference voltage level V.sub.REF at the other input node and produces an output signal when the voltage level at the one input node excesses the reference voltage level V.sub.REF. The output signal of the comparator 3 is supplied from an output node of the comparator 3 to a set node of the flip-flop circuit 4 and causes the flip-flop circuit 4 to change from the reset state to the set state.
In operation, when a control signal appears at the control node 16, the MOS field-effect transistor 6 turns on, then the oscillation circuit 1 is activated to produce an oscillation signal or a raw pulse train. In the initial stage of the activation, the raw pulse train includes pulses each having a pulse height lower than the reference voltage level V.sub.REF, so that the comparator 3 does not produce the output signal. This results in that the flip-flop circuit 4 remains in the reset state. When the flip-flop circuit 4 is in the reset state, the flip-flop circuit 4 does not produce an output signal Q, then the AND gate 5 can not produce any pulse train. However, if the oscillation circuit 1 produces a raw pulse train consisting of sufficiently developed pulses, each of the pulses has a pulse height which excesses the reference voltage level V.sub.REF, then the comparator 3 produces the output signal which is supplied to the set node of the flip-flop circuit 4. With the output signal supplied from the comparator 3, the flip-flop circuit 4 is changed from the reset state to the set state, thereby producing the output signal Q which is supplied to the AND gate 5. The output signal Q allows the AND gate 5 to produce the pulse train which consists of the pulses each having the sufficient pulse height.
The voltage divider 2, comparator 3, the flip-flop circuit 4 and the AND gate thus forms in combination an eliminating circuit which prohibits the pulse generating circuit from production of a pulse train including a pulse with an insufficient pulse height.
However, a problem is encountered in the prior-art pulse generating circuit in producing a pulse train including a pulse with an insufficient pulse height when the voltage level on the source line 9 is decreased. In detail, the output node 15 is coupled to the source line 9 and the ground line 10 through the MOS field-effect transistors 6 and 8, respectively, so that the output node 15 is varied in voltage level by changing the voltage level on the source line 9 as indicated by plots A in FIG. 2 of the drawings. On the other hand, the reference voltage V.sub.REF is determined by proportional allotment based on the resistance values of the resistors 18 and 19. Then, the reference voltage V.sub.REF is varied by changing the voltage level on the source line 9 as indicated by plots B in FIG. 2. Comparing plots A with plots B, plot A intersects plots B at point C. If the reference voltage V.sub.REF is selected on the assumption that the source line 9 is higher in voltage level than point C at all times, the comparator 3 produces the output signal under the reduction of voltage level on the source line 9 below point C even if a raw pulse train consists of pulses each having an insufficient pulse height. For example, when the source line 9 is supplied from a battery, the above problem would take place with time.
It is therefore an important object of the present invention to provide a pulse generating circuit operative to produce a pulse train with a sufficient pulse height.
It is another important object of the present invention to provide a pulse generating circuit which is free from the fluctuation of voltage level on a source of voltage.